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1 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs4226 surround sound codec features l stereo 20-bit a/d converters l six 20-bit d/a converters l s/pdif receiver ac-3 & mpeg auto-detect capability l 108 db dac signal-to-noise ratio (eiaj) l mono 20-bit a/d converter l programmable input gain & output attenuation l on-chip anti-aliasing and output smoothing filters l de-emphasis for 32 khz, 44.1 khz, 48 khz description the cs4226 is a single-chip codec providing stereo an- alog-to-digital and six digital-to-analog converters using delta-sigma conversion techniques. this +5 v device also contains volume control independently selectable for each of the six d/a channels. an s/pdif receiver is included as a digital input channel. applications include dolby pro-logic, thx, dts and dolby digital ac-3 home theater systems, dsp based car audio systems, and other multi-channel applications. the cs4226 is packaged in a 44-pin plastic tqfp. ordering information CS4226-KQ -10 to +70 c 44-pin tqfp cs4226-bq -40 to +85 c 44-pin tqfp cdb4226 evaluation board i scl/cclk dem sda/cdout vd+ aout1 lrck sclk sdin1 sdout1 serial audio data interface control port digital filters dac#1 right adc left adc volume control analog low pass and output stage va+ aout2 ain1l ain1r sdin2 sdout2 ovl/err dac#4 dac#2 dac#3 dem mux clock osc/ divider clkout xti xto pll filt volume control volume control volume control lrckaux/rx3 sclkaux/rx2 dgnd1 dgnd2 s/pdif rx/auxiliary input input gain aout3 aout4 voltage reference ain2l/freq0 ain2r/freq1 ain3l/autodata ain3r/audio input mux agnd2 sdin3 pdn ad1/cdin ad0/cs i 2 c/spi cmout dac#6 dac#5 volume control volume control aout5 aout6 mono adc ainaux agnd1 rx1 dataux/rx4 hold/rubit digital filters sep 98 ds188f1
cs4226 2 ds188f1 table of contents characteristics/specifications ............................................................ 3 analog characteristics................................................................... 3 switching characteristics ............................................................. 5 switching characteristics - control port ............................. 6 s/pdif receiver characteristics................................................... 7 absolute maximum ratings .............................................................. 8 recommended operating conditions .......................................... 8 digital characteristics.................................................................... 8 functional description .......................................................................... 10 overview ................................................................................................... 10 analog inputs ............................................................................................ 10 line level inputs ................................................................................ 10 adjustable input gain ......................................................................... 11 high pass filter .................................................................................. 11 analog outputs ......................................................................................... 11 line level outputs ............................................................................. 11 output level attenuator ..................................................................... 11 clock generation ...................................................................................... 12 clock source ...................................................................................... 12 master clock output .......................................................................... 13 synchronization .................................................................................. 13 digital interfaces ....................................................................................... 13 audio dsp serial interface signals .................................................... 13 audio dsp serial interface formats .................................................. 13 auxiliary audio port signals ............................................................... 15 auxiliary audio port formats .............................................................. 15 s/pdif receiver ................................................................................ 15 ac-3/mpeg auto detection ............................................................... 16 control port signals .................................................................................. 16 spi mode ........................................................................................... 16 i 2 c mode ............................................................................................ 17 control port bit definitions ................................................................. 17 power-up/reset/power down mode ......................................................... 18 dac calibration ........................................................................................ 18 de-emphasis ............................................................................................ 18 hold function ......................................................................................... 19 power supply, layout, and grounding ..................................................... 19 adc and dac filter response plots ....................................................... 19 register description ............................................................................... 21 pin description ............................................................................................ 29 parameter definitions ............................................................................. 34 package dimensions .................................................................................. 35 advanced product information describes products which are in development and subject to development changes. cirrus logic, inc . has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subjec t to change without notice and is provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic , inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus l ogic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of prod ucts of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners wh ich may be reg- istered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com . dolby and ac-3 are registered trademarks, dolby pro-logic is a trademark of dolby laboratories licensing corporation. dts is a registered trade- mark of dts, inc.. thx is a registered trademark of lucasarts entertainment company. i 2 c is a registered trademark of philips semiconductor.
cs4226 ds188f1 3 characteristics/specifications analog characteristics (t a = 25c; va+, vd+ = +5v; full scale input sine wave, 990.52 hz; fs = 44.1 khz (pll in use); measurement bandwidth is 20 hz to 20 khz; local components as shown in figure 1; spi mode, format 3, unless otherwise specified.) notes: 1. referenced to typical full-scale differential input voltage (2vrms). 2. input resistance is for the input selected. non-selected inputs have a very high (>1m w ) input resistance. the input resistance will vary with gain value selected, but will always be greater than the min. value specified 3. filter characteristics scale with output sample rate. 4. the analog modulator samples the input at 5.6448 mhz for an output sample rate of 44.1 khz. there is no rejection of input signals which are multiples of the sampling frequency (n 5.6448 mhz 20.0 khz where n = 0,1,2,3...). 5. group delay for fs = 44.1 khz, t gd = 15/44.1 khz = 340 m s parameter symbol CS4226-KQ cs4226-bq units min typ max min typ max analog input characteristics - minimum gain setting (0 db) differential input; unless otherwise specified. adc resolution stereo audio channels mono channel 16 16 - - 20 20 16 16 - - 20 20 bits bits total harmonic distortion thd 0.003 - 0.003 - % dynamic range (a weighted, stereo) (unweighted, stereo) (a weighted, mono) 92 - 89 95 92 - - - - 90 - 87 93 90 - - - - db db db total harmonic -1 db, stereo (note 1) distortion + noise -1 db, mono (note 1) thd+n - - -88 - -82 -72 - - -86 - -80 -70 db db interchannel isolation - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db programmable input gain span 8 9 10 8 9 10 db gain step size 2.7 3 3.3 2.7 3 3.3 db offset error (with high pass filter) - - 0 - - 0 lsb full scale input voltage (single ended): 0.90 1.0 1.10 0.90 1.0 1.10 vrms gain drift - 100 - - 100 - ppm/c input resistance (note 2) 10 - - 10 - - k w input capacitance - - 15 - - 15 pf cmout output voltage - 2.3 - - 2.3 - v a/d decimation filter characteristics passband (note 3) 0.02 - 20.0 0.02 - 20.0 khz passband ripple - - 0.01 - - 0.01 db stopband (note 3) 27.56 - 5617.2 27.56 - 5617.2 khz stopband attenuation (note 4) 80 - - 80 - - db group delay (fs = output sample rate) (note 5) t gd - 15/fs - - 15/fs - s group delay variation vs. frequency d t gd --0--0 m s
cs4226 4 ds188f1 analog characteristics (continued) notes: 6. the passband and stopband edges scale with frequency. for input word rates, fs, other than 44.1 khz, the 0.01 db passband edge is 0.4535fs and the stopband edge is 0.5465fs. 7. digital filter characteristics. 8. measurement bandwidth is 10 hz to 3 fs. parameter symbol CS4226-KQ cs4226-bq units min typ max min typ max high pass filter characteristics frequency response: -3 db (note 3) -0.13 db - - 3.4 20 - - - - 3.4 20 - - hz hz phase deviation @ 20 hz (note 3) - 10 - - 10 - deg. passband ripple - - 0 - - 0 db analog output characteristics - minimum attenuation, 10 k, 100 pf load; unless otherwise specified. dac resolution 16 - 20 16 - 20 bits signal-to-noise/idle (dac muted, a weighted) channel noise 101 108 - 99 106 - db dynamic range (dac not muted, a weighted) (dac not muted, unweighted) 93 - 98 95 - - 91 - 96 93 - - db db total harmonic distortion thd - 0.003 - - 0.003 - % total harmonic distortion + noise (stereo) thd+n - -88 -83 - -86 -81 db interchannel isolation - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db attenuation step size (all outputs) 0.7 1 1.3 0.7 1 1.3 db programmable output attenuation span -84 -86 - -84 -86 - db offset voltage (relative to cmout) - 15 - - 15 - mv full scale output voltage 0.92 1.0 1.08 0.92 1.0 1.08 vrms gain drift - 100 - - 100 - ppm/c out-of-band energy (fs/2 to 2fs) - -60 - - -60 - dbfs analog output load resistance: capacitance: 10 - - - - 100 10 - - - - 100 k w pf combined digital and analog filter characteristics frequency response 10 hz to 20 khz - 0.1 - - 0.1 - db deviation from linear phase - 0.5 - - 0.5 - deg. passband: to 0.01 db corner (notes 6, 7) 0 - 20.0 0 - 20.0 khz passband ripple (note 7) - - 0.01 - - 0.01 db stopband (notes 6 ,7) 24.1 - - 24.1 - - khz stopband attenuation (note 8) 70 - - 70 - - db group delay (fs = input word rate) (note 5) tgd - 16/fs - - 16/fs - s analog loopback performance signal-to-noise ratio (ccir-2k weighted, -20 db input) ccir-2k -71- -71- db power supply power supply current operating power down - - 90 1 113 3 - - 90 1 115 3 ma ma power supply rejection (1 khz, 10 mv rms ) - 45 - - 45 - db
cs4226 ds188f1 5 switching characteristics (t a = 25c; va+, vd+ = +5v 5%, outputs loaded with 30 pf) notes: 9. after powering up the cs4226, pdn should be held low until the power supply is settled. parameter symbol min typ max units audio adc's & dac's sample rate fs 4 - 50 khz xti frequency (xti = 256, 384, or 512 fs) 1.024 - 26 mhz xti pulse width high xti = 512 fs xti = 384 fs xti = 256 fs 10 21 31 - - - - - - ns ns ns xti pulse width low xti = 512 fs xti = 384 fs xti = 256 fs 10 21 31 - - - - - - ns ns ns pll clock recovery frequency rx, xti, lrck, lrckaux 30 - 50 khz xti jitter tolerance - 500 - ps pdn low time (note 9) 500 - - ns sclk falling edge to sdout output valid (dsck = 0) t dpd -- ns lrck edge to msb valid t lrpd -- 40ns sdin setup time before sclk rising edge (dsck=0) t ds -- 25ns sdin hold time after sclk rising edge (dsck=0) t dh -- 25ns master mode sclk period t sck --ns sclk falling to lrck edge (dsck=0) t mslr -10 - ns sclk duty cycle - 50 - % slave mode sclk period t sckw --ns sclk high time t sckh 40 - - ns sclk low time t sckl 40 - - ns sclk rising to lrck edge (dsck=0) t lrckd 20 - - ns lrck edge to sclk rising (dsck=0) t lrcks 40 - - ns 1 384 () fs ------------------- - 20 + 1 256 () fs ------------------- - 1 128 () fs ------------------- - t mslr sclk* sclkaux* (output) lrck lrckaux (output) sdout1 sdout2 t sck audio ports master mode timing sckh sckl sckw t t t msb msb-1 *sclk, sclkaux shown for dsck = 0 and asck = 0. sclk & sclkaux inverted for dsck = 1 and asck = 1, respectively. t dpd sdout1 sdout2 lrckaux (input) lrck sclk* sclkaux* (input) sdin1 sdin2 dataux dh t ds t lrpd t lrcks t lrckd t sdin3 audio ports slave mode and data i/o timing
cs4226 6 ds188f1 switching characteristics - control port (ta = 25c vd+, va+ = 5v 5%; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 30 pf) notes: 10. data must be held for sufficient time to bridge the transition time of cclk. 11. for f sck < 1 mhz parameter symbol min max units spi mode (spi/i 2 c = 0) cclk clock frequency f sck -6mhz cs high time between transmissions t csh 1.0 m s cs falling to cclk edge t css 20 ns cclk low time t scl 66 ns cclk high time t sch 66 ns cdin to cclk rising setup time t dsu 40 ns cclk rising to data hold time (note 10) t dh 15 ns cclk falling to cdout stable t pd 45 ns rise time of cdout t r1 25 ns fall time of cdout t f1 25 ns rise time of cclk and cdin (note 11) t r2 100 ns fall time of cclk and cdin (note 11) t f2 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh
cs4226 ds188f1 7 switching characteristics - control port (t a = 25c; vd+, va+ = 5v 5%; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 30 pf) notes: 12. i 2 c is a registered trademark of philips semiconductors. 13. data must be held for sufficient time to bridge the 300 ns transition time of scl. s/pdif receiver characteristics (rx1, rx2, rx3, rx4 pins only; vd+, va+ = 5v 5%) notes: 14. clkout jitter is for 256fs selected as output frequency measured from falling edge to falling edge. jitter is greater for 384fs and 512fs as selected output frequency. 15. for clkout frequency equal to 1fs, 384fs, and 512fs. see master clock output section. parameter symbol min max units i 2 c ? mode (spi/i 2 c = 1) (note 12) scl clock frequency f scl -100khz bus free time between transmissions t buf 4.7 m s start condition hold time (prior to first clock pulse) t hdst 4.0 m s clock low time t low 4.7 m s clock high time t high 4.0 m s setup time for repeated start condition t sust 4.7 m s sda hold time from scl falling (note 13) t hdd 0 m s sda setup time to scl rising t sud 250 ns rise time of both sda and scl lines t r 1 m s fall time of both sda and scl lines t f 300 ns setup time for stop condition t susp 4.7 m s parameter symbol min typ max units input resistance z n -10- k w input voltage v th 200 - - mvpp input hysteresis v hyst -50- mv input sample frequency f s 30 - 50 khz clkout jitter (note 14) - 200 - ps rms clkout duty cycle (high time/cycle time) (note 15) 40 50 60 % t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl
cs4226 8 ds188f1 absolute maximum ratings (agnd, dgnd = 0 v, all voltages with respect to 0 v.) notes: 16. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 17. the maximum over or under voltage is limited by the input current. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0 v, all voltages with respect to 0 v.) digital characteristics (t a = 25 c; va+, vd+ = 5 v 5%) parameter symbol min typ max units power supplies digital analog vd+ va+ -0.3 -0.3 - - 6.0 6.0 v v input current (note 16) - - 10 ma analog input voltage (note 17) -0.7 - (va+)+0.7 v digital input voltage (note 17) -0.7 - (vd+)+0.7 v ambient temperature (power applied) -55 - +125 c storage temperature -65 - +150 c parameter symbol min typ max units power supplies digital |(va+)-(vd+)|<0.4 v analog vd+ va+ 4.75 4.75 5.0 5.0 5.25 5.25 v v operating ambient temperature CS4226-KQ cs4226-bq t a -10 -40 25 25 70 85 c c parameter symbol min typ max units high-level input voltage (except rx1) v ih 2.8 - (vd+)+0.3 v low-level input voltage (except rx1) v il -0.3 - 0.8 v high-level output voltage at i 0 = -2.0 ma v oh (vd+)-1.0 - - v low-level output voltage at i 0 = 2.0 ma v ol --0.4v input leakage current (digital inputs) - - 10 m a output leakage current (high-impedance digital outputs) - - 10 m a
cs4226 ds188f1 9 +5v supply ferrite bead + 1 m f 0.1 m f 19 2.0 w + 1 m f 0.1 m f 40 va+ vd+ agnd1, 2 dgnd1, 2 filt xto xti r filt c filt c rip 17 c1** c2** 29 28 39 41 20 18 21 * optional if analog inputs biased to within 1% of cmout aout1 22 aout2 23 aout3 24 aout4 25 aout5 26 aout6 3 4 6 5 microcontroller scl/cclk sda/cdout ad0/cs ad1/cdin 34 33 32 36 audio dsp sdin1 sdin2 sdin3 sdout1 35 37 38 31 30 sdout2 lrck sclk clkout ovl/err r s r s 16 15 10 m f 1 m f cmout 14 10 m f to optional input and output buffers ain1l 13 10 m f ain1r 11 10 m f ain2l/freq0 12 10 m f ain2r/freq1 10 10 m f ain3l/autodata 9 10 m f ain3r/audio 42 rx1 1 44 43 dataux/rx4 lrckaux/rx3 sclkaux/rx2 r s r s ainaux digital audio source 8 pdn 7 i c/spi mode setting 2 all unused analog inputs should be left floating. cs4226 2 hold/rubit 27 dem analog filter analog filter analog filter analog filter analog filter analog filter * * * * * * * from optional input buffer r ** x1 r ** x2 ** r x1 r x2 c2 c1 40 pf 40 pf 10 pf 40 pf 300 k w short 10 m w open 1xfs 256, 384, 512xfs + r = 50 w s r = 475 w d r s r s r s r s 100 pf r s r s r d r d r d all unused digital inputs should be tied to dgnd. c filt r filt c rip 15 nf 43 k w 1.5 nf 180 nf 3.3 k w 18 nf normal high loop current 100 pf 100 pf 100 pf ? ? ? ? ? only needed when inputs are used for s/pdif. figure 1. recommended connection diagram
cs4226 10 ds188f1 functional description overview the cs4226 has 2 channels of 20-bit analog-to- digital conversion and 6 channels of 20-bit digital- to-analog conversion. a mono 20-bit adc is also provided. all adcs and dacs are delta-sigma converters. the stereo adc inputs have adjustable input gain, while the dac outputs have adjustable output attenuation. the device also contains an s/pdif receiver capable of receiving compressed ac-3/mpeg or uncompressed digital audio data. digital audio data for the dacs and from the adcs is communicated over separate serial ports. this allows concurrent writing to and reading from the device. the cs4226 functions are controlled via a serial microcontroller interface. figure 1 shows the recommended connection diagram for the cs4226. analog inputs line level inputs ain1r, ain1l, ain2r, ain2l, ain3r, ain3l and ainaux are the line level input pins (see fig- ure 1). these pins are internally biased to the cmout voltage. a 10 m f dc blocking capacitor placed in series with the input pins allows signals centered around 0 v to be input to the cs4226. fig- ure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to atten- uate the standard line level of 2 vrms to 1 vrms. the cmout reference level is used to bias the op- amps to approximately one half the supply voltage. with this input circuit, the 10 m f dc blocking caps in figure 1 may be omitted. any remaining dc off- set will be removed by the internal high-pass fil- ters. selection of stereo the input pair (ain1l/r, ain2l/r or ain3l/r) for the 20-bit adc's is ac- complished by setting the ais1/0 bits (adc analog input mux control), which are accessible in the adc control byte. on-chip anti-aliasing filters follow the input mux providing anti-aliasing for all input channels. the analog inputs may also be configured as differ- ential inputs. this is enabled by setting bits ais1/0=3. in the differential configuration, the left channel inputs reside on pins 10 and 11, and the right channel inputs reside on pins 12 and 13 as de- scribed in table 1 below. in differential mode, the full scale input level is 2 vrms. the analog signal is input to the mono adc via the ainaux pin. independent muting of both the stereo adc's and the mono adc is possible through the adc con- trol byte with the mutr, mutl and mutm bits. single-ended pin # differential inputs ain3l pin 10 ainl+ ain3r pin 9 unused ain2l pin 11 ainl- ain2r pin 12 ainr- ain1l pin 14 unused ain1r pin 13 ainr+ table 1. single-ended vs differential input pin assignments + - 100 pf 10 k 20 k + - 10 k 100 pf 5 k 20 k line in right line in left cmout ainxr ainxl 0.47 m f 3.3 m f 3.3 m f example op-amps are mc34074 or mc33078 figure 2. optional line input buffer
cs4226 ds188f1 11 adjustable input gain the signals from the line inputs are routed to a pro- grammable gain circuit which provides up to 9 db of gain in 3 db steps. the gain is adjustable through the input control byte. right and left channel gain settings are controlled independently with the gnr1/0 and gnl1/0 bits. level changes occur immediately on register updates. to mini- mize audible artifacts, level changes should be done with the channel muted. the adc status report byte provides feedback of input level for each adc channel. this register continously monitors the adc output and records the peak output level since the last register read. reading this register causes it to reset to 0 and peak monitoring begins again. high pass filter the operational amplifiers in the input circuitry driving the cs4226 may generate a small dc offset into the a/d converter. the cs4226 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc lev- el, possibly yielding "clicks" when switching be- tween devices in a multichannel system. the characteristics of this first-order high pass fil- ter are outlined table 2 below for an output sample rate of 44.1 khz. this filter response scales linearly with sample rate. analog outputs line level outputs the cs4226 contains an on-chip buffer amplifier producing single-ended outputs capable of driving 10 k w loads. each output (a out 1-6) will produce a nominal 2.83 vpp (1 vrms) output with a 2.3 volt quiescent voltage for a full scale digital input. the recommended off-chip analog filter is a 2nd order butterworth with a -3 db corner at fs, see figure 3. this filter provides out-of-band noise attenuation along with a gain of 2, providing a 2 vrms output signal. a 3rd order butterworth filter with a -3db corner at 0.75 fs can be used if greater out of band noise filtering is desired. the cs4226 dac inter- polation filter is a linear phase design which has been pre-compensated for an external 2nd order butterworth filter to provide a flat frequency re- sponse and linear phase response over the pass- band. if this filter is not used, small frequency response magnitude and phase errors will occur. output level attenuator the dac outputs are each routed through an atten- uator which is adjustable in 1 db steps. output at- tenuation is available through the output attenuator data bytes. level changes are imple- mented in the analog domain such that the noise is attenuated by the same amount as the signal , until the residual output noise is equal to the noise floor in the mute state; at this point attenation is imple- mented in the digital domain. the change from an- alog to digital attenuation occurs at -23 db. level changes only take effect on zero crossings to mini- mize audible artifacts. if there is no zero crossing, then the requested level change will occur after a time-out period between 512 and 1024 frames (11.6 ms to 23.2 ms at 44.1 khz frame rate). there is a separate zero crossing detector for each chan- nel. each acc bit (acceptance bit) in the dac status report byte gives feedback on when a vol- ume control change has taken effect. this bit goes high when a new setting is loaded and returns low when it has taken effect. volume control changes can be instantaneous by setting the zero crossing disable (zcd) bit in the dac control byte to 1. each output can be independently muted via mute control bits, mut6-1, in the dac control byte. frequency response -3db @ 3.4 hz -0.13 db @ 20 hz phase deviation 10 degrees @ 20 hz passband ripple none table 2. high pass filter characteristics
cs4226 12 ds188f1 the mute also takes effect on a zero-crossing or af- ter a timeout. in addition, the cs4226 has an op- tional mute on consecutive zeros feature, where all dac outputs will mute if they receive between 512 and 1024 consecutive zeros (or -1 code) on all six channels. a single non-zero value will unmute the dac outputs. this feature can be disabled with the mutc bit in the dac control byte. when using the internal pll as the clock source, all dacs will instantly mute when the pll detects an error. clock generation the master clock to operate the cs4226 may be generated by using the on-chip inverter and an ex- ternal crystal, by using the on-chip pll, or by us- ing an external clock source. in all modes it is required to have sclk and lrck synchronous to the selected master clock. clock source the cs4226 requires a high frequency master clock to run the internal logic. the clock source bits, cs0/1/2 in clock mode byte, determine the source of the clock. a high frequency crystal can be connected to xti and xto, or a high frequency clock can be applied to xti. in both these cases, the internal pll is disabled, and the vco turns off. the externally supplied high frequency clock can be 256 fs, 384 fs or 512 fs; this is set by the ci0/1 bits in the clock mode byte. when using the on- chip crystal oscillator, external loading capacitors are required, see figure 1. high frequency crystals (>8mhz) should be parallel resonant, fundamental mode and designed for 20 pf loading (equivalent to 40 pf to ground on each leg). alternatively, the on-chip pll may be used to gen- erate the required high frequency clock. the pll input clock is 1 fs, and may be input from lrck- aux, lrck, or from xti/xto. in this last case, a 1 fs clock may be input into xti, or a 1 fs crystal attached across xti/xto. when an external 1 fs crystal is attached, extra components will be re- quired, see figure 1. the pll will lock onto a new 1 fs clock in about 90 ms. if the pll input clock is removed, the vco will drift to the low frequency end of its frequency range. the pll can also be used to lock to an s/pdif data source on rx1, rx2, rx3, or rx4. source selec- tion is accomplished with the cs2/1/0 bits in the clock mode byte. the pll will lock to an s/pdif source in about 90 ms. finally, the pll has two filter loop current modes, normal and high current, that are selected via the lc bit in the converter control byte. in the normal mode, the loop current is 25 m a. in the high current _ 22 k w 150pf 3.9 k w 11 k w 1000pf + c mout 5 k w 0.47 m f example op-amps are mc33078 _ 5.85 k w 560 pf 1.21 k w 1.1 k w 5600 pf + c mout 5 k w 0.47 m f a out 4.75 k w 5600 pf 2-pole butterworth filter 3-pole butterworth filter a out figure 3.
cs4226 ds188f1 13 mode, the loop current is 300 m a. the high current mode allows the use of lower impedance filter components which minimizes the influences of board contamination. see the table in figure 1 for filter component values in each mode. master clock output clkout is a master clock output provided to al- low synchronization of external components. available clkout frequencies of 1 fs, 256 fs, 384 fs, and 512 fs, are selectable by the co0/1 bits of the clock mode byte. generation of clkout for 384 fs and 512 fs is accomplished with an on chip clock multiplier and may contain clock jitter. the source of the 256 fs clkout is the output of the pll or a divided down clock from the xti/xto input. if 384 fs is chosen as the input clock at xti and 256 fs is cho- sen as the output, clkout will have approxi- mately a 33% duty cycle. in all other cases clkout will typically have a 50% duty cycle. synchronization the dsp port and auxiliary port must operate syn- chronously to the cs4226 clock source. the serial port will force a reset of the data paths in an attempt to resynchronize if non-synchronous data is input to the cs4226. it is advisable to mute the dacs when changing from one clock source to another to avoid the output of undesirable audio signals as the cs4226 resynchronizes. digital interfaces there are 3 digital audio interface ports: the audio dsp port, the auxiliary digital audio port, and the s/pdif reciever. the serial data is represented in 2's complement format with the msb-first in all formats. audio dsp serial interface signals the serial interface clock, sclk, is used for trans- mitting and receiving audio data. the active edge of sclk is chosen by setting the dsck bit in the dsp port mode byte. sclk can be generated by the cs4226 (master mode) or it can be input from an external sclk source (slave mode). mode se- lection is set with the dms1/0 bits in the dsp port mode byte. the number of sclk cycles in one system sample period is programmable to be 32, 48, 64, or 128 by setting the dck1/0 bits in the dsp port mode byte. the left/right clock (lrck) is used to indicate left and right data and the start of a new sample pe- riod. it may be output from the cs4226, or it may be generated from an external controller. the fre- quency of lrck must be equal to the system sam- ple rate, fs. sdin1, sdin2, and sdin3 are the data input pins, each of which drive a pair of dacs. sdout1 and sdout2 can carry the output data from the two 20-bit adc's, the mono adc, the auxiliary digital audio port, and the s/pdif receiver. selection de- pends on the is1/0 bits in the adc control byte. the audio dsp port may also be configured so that all 6 dac's data is input on sdin1, and all 3 adc's data is output on sdout1. table 3 outlines the serial interface ports. audio dsp serial interface formats the audio dsp port supports 7 alternate formats, shown in figures 4, 5, and 6. these formats are chosen through the dsp port mode byte with the ddf2/1/0 bits. formats 5 and 6 are single line data modes where all dac channels are combined onto a single input dac inputs sdin1 left channel right channel single line dac #1 dac #2 all 6 dac channels sdin2 left channel right channel dac #3 dac #4 sdin3 left channel right channel dac #5 dac #6 table 3. dsp serial interface ports
cs4226 14 ds188f1 lrck format 0, 1, 2: sclk sdin format 0: m = 20 format 1: m = 18 format 2: m = 16 lsb lsb msb lsb msb left right m sclks m sclks lrck format 3: sclk sdin msb lsb left right msb lsb msb lrck format 4: sclk sdin msb lsb left right msb lsb note: sclk shown for dsck = 0. sclk inverted for dsck = 1. figure 4. audio dsp and auxiliary port data input formats lrck format 0, 1, 2: sclk sdout format 0: m = 20 format 1: m = 18 format 2: m = 16 lsb lsb msb lsb msb left right m sclks m sclks lrck format 3: sclk sdout msb lsb left right msb lsb msb lrck format 4: sclk sdout msb lsb left right msb lsb note: sclk shown for dsck = 0. sclk inverted for dsck = 1. figure 5. audio dsp port data output formats lrck format 5: sclk sdin1 lsb msb 20 clks 64 sclks 64 sclks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac #1 dac #3 dac #5 dac #2 dac #4 dac #6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks sdout1 sdout2 sdout1 sdout2 20 clks 20 clks 20 clks sdout1 lrck format 6: sclk sdin1 lsb msb 32 clks 128 sclks 128 sclks dac #1 dac #3 dac #5 32 clks 32 clks 32 clks sdout1 sdout2 32 clks sdout1 lsb msb lsb msb lsb msb 32 clks dac #2 dac #4 dac #6 32 clks 32 clks 32 clks sdout1 sdout2 32 clks lsb msb lsb msb (master mode only) (out) (out) figure 6. one data line modes
cs4226 ds188f1 15 and all adc channels are combined onto a single output. format 6 is available in master mode only. see figure 6 for details. auxiliary audio port signals the auxiliary port provides an alternate way to in- put digital audio signals into the cs4226, and al- lows the cs4226 to synchronize the system to an external digital audio source. this port consists of serial clock, data and left/right clock pins named, sclkaux, dataux and lrckaux. the auxiliary audio port input is output on sdout1 when the is bits are set to 1 or 2 in the adc control byte. additionally, setting is to 2 routes the stereo adc outputs to sdout2. there is approximately a two frame delay from dataux to sdout1. when the auxiliary port is used, the frequency of lrckaux must equal to the system sample rate, fs, but no particular phase relationship is required. de-emphasis and muting on error conditions can be performed on input data to the auxiliary audio port; this is controlled by the auxiliary port control byte. auxiliary audio port formats data input on dataux is clocked into the part by sclkaux using the format selected in the auxil- iary port mode byte. the auxiliary audio port sup- ports the same 5 formats as the audio dsp port in multi-data line mode. lrckaux is used to indi- cate left and right data samples, and the start of a new sample period. sclkaux and lrckaux may be output from the cs4226, or they may be generated from an external source, as set by the ams1/0 control bits in the auxiliary port mode byte. s/pdif receiver the cs4226 reconfigures its auxiliary digital audio port as an s/pdif receiver if cs2/1/0 in the clock mode byte are set to be 4, 5, 6, or 7. in this mode rx1, rx2, rx3, or rx4 can be chosen as the s/pdif input source. the pll will lock to the requested data source and setting is1/0 = 1 or 2 in the adc control byte routes the recovered output to sdout1 (channel a to left, channel b to right). all 24 received data bits will pass through the part to sdout1 except when the serial port is configured with 32 sclk's per frame or in format 5. for these cases, the 16 or 20 msb's respectively will be output. the error flags are reported in the receiver status byte. the lock bit indicates whether the pll is locked to the incoming s/pdif data. parity, bi- phase, or validity errors (par=1, bip=1 or v=1) will cause the last valid data sample to be held at the receiver input until the error condition no long- er is present (see hold section). mute on extended hold can also be enabled through the auxiliary port control byte (see hold section). other error flags include confidence, conf, and cyclic redundancy check, crc. the conf flag oc- curs when the received data eye opening is less than half a bit period. this indicates that the quality of the transmission link is poor and does not meet the digital audio interface standards. the crc flag is updated at the beginning of a channel status block and is only valid when the professional for- mat of channel status data is received. this error indicates when the cs4226 calculated crc value does not match the crc byte of the received chan- nel status block. the ovl/err pin will go high to flag an error. it is a latched logical or of the parity, biphase, va- lidity, and lock error flags in the receiver status byte which is reset at the end of each frame. how- ever, parity, biphase, or validity errors can be masked from the pin by clearing the pm, bm, and vm bits respectively, of the input control byte. the first four bytes of the channel status block for both channel a and b can be accessed in the re- ceiver channel status bytes. when the cv bit is
cs4226 16 ds188f1 high, these bytes are being updated and may be in- valid. additionally, the audio/non-audio, ac- 3/mpeg data stream indicator and sampling fre- quency channel status bits may be output to pins 9, 10, 11 and 12, respectively, see table 4. this is ac- complished by setting the csp bit to 1 in the aux- iliary status output byte. the freq0/1 channel status bit outputs are decoded from the sampling frequency channel status bits after first referencing channel status byte 0, bit 0 (pro or consumer bit) which indicates the appropriate location of these bits in the channel status data stream. the received user bit is output on the hold/ru- bit pin if the hpc bit in the aux port control byte is set to 1. it can be sampled with the rising or falling edge of lrck if the audio dsp port is in master mode. ac-3/mpeg auto detection for ac-3/mpeg applications, it is important to know whether the incoming s/pdif data stream is digital audio or compressed ac-3/mpeg data. this information is typically conveyed by setting channel status bit 1 (audio/non-audio bit), but some ac-3/mpeg sources may not strictly adhere to this convention and the bit may not be properly set. the cs4226 s/pdif receiver has the capability to auto- matically detect whether the incoming data is a compressed ac-3/mpeg input. this is accom- plished by looking for an ac-3/mpeg 96-bit sync code consisting of six 16-bit words. the 96-bit sync code consists of: 0x0000, 0x0000, 0x0000, 0x0000, 0xf872, and 0x4e1f. when the sync code is detected, the autodata indicator (pin 10) will go high. if no additional sync codes are detect- ed within the next 4096 frames, the autodata indicator pin will return low until another sync code is detected. control port signals the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i 2 c, with the cs4226 as a slave device. the spi mode is selected by setting the i 2 c/spi pin low, and i 2 c is selected by setting the i 2 c/spi pin high. the state of this pin is continuously monitored. spi mode in spi mode, cs is the cs4226 chip select signal, cclk is the control port bit clock, (input into the cs4226 from the microcontroller), cdin is the in- put data line from the microcontroller, cdout is the output data line to the microcontroller, and the chip address is 0010000. data is clocked in on the rising edge of cclk and out on the falling edge. figure 7 shows the control port timing in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and they must be 0010000. the eighth bit is a read/write indicator (r/w ), which should be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into register designated by the map. during writes, the cdout output stays in the high impedance state. it may be externally pulled high or low with a 47 k w resistor. the cs4226 has a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, then the map will stay constant for audio pin 9 0 - audio data 1 - non-audio data autodata pin 10 0 - no preamble detected in last 4096 frames 1 - preamble detected freq0/1 pin 11/12 00 - 44.1 khz 01 - 48 khz 10 - reserved 11 - 32 khz table 4. s/pdif receiver status outputs
cs4226 ds188f1 17 successive reads or writes. if incr is set to a 1, then map will auto increment after each byte is read or written, allowing block reads or writes of successive registers. to read a register, the map has to be set to the cor- rect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the auto map increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecu- tively. i 2 c mode in i 2 c mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 8. there is no cs pin. pins ad0, ad1 form the partial chip address. the upper 5 bits of the 7 bit address field must be 00100. to commu- nicate with a cs4226, the lsbs of the chip address field, which is the first byte sent to the cs4226, should match the settings of the ad1, ad0 pins. the eighth bit of the address bit is the r/w bit (high for a read, low for a write). the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a write, the next byte is the data to be written to the register pointed to by the map. if the operation is a read, the contents of the register pointed to by the map will be output. setting the auto increment bit in map, allows successive reads or writes of con- secutive registers. each byte is separated by an ac- knowledge bit. i 2 c bus is a registered trademark of philips semiconductors. control port bit definitions all registers can be written and read back, except the dac status report byte, adc status report byte, receiver status byte, and the receiver chan- nel status bytes, which are read only. see the bit definition tables for bit assignment information. map msb lsb data byte 1 byte n r/w r/w high impedance map = memory address pointer address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 figure 7. control port timing, spi mode sda scl 00100 addr ad1-0 r/w start ack data 1-8 ack data 1-8 ack stop note 1: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, i 2 c mode
cs4226 18 ds188f1 power-up/reset/power down mode upon power up, the user should hold pdn =0 until the systems power supply has stabilized. in this state, the control port is reset to its default settings. when pdn goes high, the device remains in a low power mode in which the control port is active, but cmout will not supply current. the desired set- tings should be loaded in while keeping the rs bit set to 1. normal operation is achieved by setting the rs bit to zero in the converter control byte. once set to 0, the part powers up and an offset calibration occurs. this process lasts approximately 50 ms. reset/power down is achieved by lowering the pdn pin causing the part to enter power down. once pdn goes high, the control port is functional and the desired settings should be loaded in while keeping the rs bit set to 1. the remainder of the chip remains in a low power reset state until the rs bit in the converter control byte is set to 0. the cs4226 will also enter a stand-by mode if the master clock source stops for approximately 10 m s or if the lrck is not synchronous to the master clock. the control port will retain its current set- tings when in stand-by mode. dac calibration output offset voltage is minimized by an internal calibration cycle. a calibration will automatically occur anytime the part comes out of reset, includ- ing the power-up reset, when the master clock source to the part changes by changing the cs or ci bits in the clock mode byte or when the pll goes out of lock and then re-locks. the cs4226 can be re-calibrated whenever de- sired. a control bit, cal, in the converter control byte, is provided to initiate a calibration. the se- quence is: 1) set cal to 1, the cs4226 sets calp to 1 and begins to calibrate. 2) calp will go to 0 when the calibration is com- pleted. additional calibrations can be implemented by set- ting cal to 0 and then to 1. de-emphasis the s/pdif receiver can be enabled to process 24 bits of received data (20 bits of audio data and four auxiliary bits) or process 20 bits of audio data (no auxiliary bits). setting dem24=0 in the auxiliary port control byte, will enable all 24 received data bits to be processed with de-emphasis when de-em- phasis is enabled. when setting dem24=1, the four auxiliary bits in the receiver data stream will pass through unchanged and only the 20 audio data bits will be processed. the cs4226 is capable of digital de-emphasis for 32, 44.1, or 48 khz sample rates. implementation of digital de-emphasis requires reconfiguration of the digital filter to maintain the filter response shown in figure 9 at multiple sample rates. the auxiliary port control byte selects the de-empha- sis control method. de-emphasis may be enabled under hardware control, using the dem pin (dem2/1/0=4,5,6), by software control using the dem bit (dem2/1/0=0,1,2,3), or by the emphasis bits in the channel status data when the s/pdif re- ceiver is chosen as the clock source (dem2/0/1=7). if no frequency information is present, the filter de- faults to 44.1 khz. gain db -10db 0db frequency t2 = 15 m s t1=50 m s f1 f2 figure 9. de-emphasis curve
cs4226 ds188f1 19 hold function if the digital audio source presents invalid data to the cs4226, the cs4226 may be configured to cause the last valid digital input sample to be held constant. holding the previous output sample oc- curs when the user asserts the hold pin (hold=1) at any time during the stereo sample pe- riod, or if a parity, biphase, or validity error occurs when receiving s/pdif data. parity, biphase, and validity errors can be independently masked so that no hold occurs. this is done using the vm, pm, and bm bits in the input control byte. during a hold condition, auxport (s/pdif) input data is ig- nored. dac outputs can be automatically muted after an extended hold period (>15 samples) by setting the moh (mute on hold) bit = 0 in the auxiliary port control byte. dacs will not be automatically muted when moh=1. when the s/pdif error con- dition is removed or the hold pin is de-asserted (hold=0), the dac outputs will return to one of two different states controlled by the umv (un- mute on valid data) bit in the auxiliary port con- trol byte. when umv=0, the dac outputs will unmute when the error is removed. when umv=1, the dacs must be unmuted in the dac control byte after the error is removed. this allows the user to unmute the dac after the invalid data has passed through the dsp. power supply, layout, and grounding as with any high resolution converter, the cs4226 requires careful attention to power supply and grounding arrangements to optimize performance. figure 1 shows the recommended power arrange- ment with va connected to a clean +5v supply. vd should be derived from va through a 2 ohm re- sistor. vd should not be used to power additional circuitry. pins 18, 20, 39 and 41, agnd and dgnd should be connected together at the cs4226. dgnd for the cs4226 should not be confused with the ground for the digital section of the system. the cs4226 should be positioned over the analog ground plane near the digital/analog ground plane split. the analog and digital ground planes must be connected elsewhere in the system. the cs4226 evaluation board, cdb4226, demon- strates this layout technique. this technique mini- mizes digital noise and insures proper power supply matching and sequencing. decoupling ca- pacitors for va, vd, and cmout should be locat- ed as close to the device package as possible. see crystal's application note an018: layout and de- sign rules for data converters and other mixed signal devices, and the cdb4226 evaluation board data sheet for recommended layout of the de- coupling components. the cs4226 will mute the analog outputs and enter the power down mode if the supply drops below approximately 4 volts. adc and dac filter response plots figures 10 through 15 show the overall frequency response, passband ripple and transition band for the cs4226 adc's and dac's.
cs4226 20 ds188f1 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 normalized frequency (fs) db 0.02 0.01 0.00 -0.01 -0.02 0.0 0.1 0.2 0.3 0.4 0.5 db normalized frequency (fs) figure 10. 20-bit adc filter response figure 11. 20-bit adc passband ripple 0.40 0.45 0.50 0.55 0.6 0.65 0.70 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 db normalized frequency (fs) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.00.10.20.30.40.50.60.70.80.91.0 db normalized frequency (fs) figure 12. 20-bit adc transition band figure 13. dac frequency response 0.02 0.01 0.00 -0.01 -0.02 0.0 0.1 0.2 0.3 0.4 0.5 db normalized frequency (fs) 0.40 0.45 0.50 0.55 0.6 0.65 0.70 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 db normalized frequency (fs) figure 14. dac passband ripple figure 15. dac transition band
cs4226 ds188f1 21 register description memory address pointer (map) map4-map0 register pointer incr auto increment control bit 0 - no auto increment 1 - auto increment on this register defaults to 01h. reserved byte (0) this byte is reserved for internal use and must be set to 00h for normal operation. this register defaults to 00h. clock mode byte (01h) cs2-cs0 sets the source of the master clock. 0 - crystal oscillator or xti at high frequency (pll disabled) 1 - pll driven by lrckaux at 1 fs 2 - pll driven by lrck at 1 fs 3 - pll driven by xti at 1 fs 4 - pll driven by rx1 data. this changes aux port to s/pdif port. 5 - pll driven by rx2 data. this changes aux port to s/pdif port. 6 - pll driven by rx3 data. this changes aux port to s/pdif port. 7 - pll driven by rx4 data. this changes aux port to s/pdif port. ci1-ci0 determines frequency of xti when pll is disabled (not used if cs 1 0) 0 - 256 fs 1 - 384 fs 2 - 512 fs 3 - not used co1-co0 sets clkout frequency 0 - 256 fs 1 - 384 fs 2 - 512 fs 3 - 1 fs this register defaults to 01h. note: if the sample rate on an input pin changes while using the pll with rx1, rx2, rx3 or rx4, the pll will not resynchronize to the new sample rate. you must either change input pins or change the clock mode byte to some- thing else and then change it back to the correct value. this will cause the pll to resync. b7 b6 b5 b4 b3 b2 b1 b0 incr 0 0 map4 map3 map2 map1 map0 b7 b6 b5 b4 b3 b2 b1 b0 0 co1 co0 ci1 ci0 cs2 cs1 cs0
cs4226 22 ds188f1 converter control byte (02h) rs chip reset (do not clear this bit until all registers have been configured as desired) 0 - no reset 1 - reset cal calibration control bit 0 - normal operation 1 - rising edge initiates calibration lc loop current 0 - normal mode, 25 m a pll loop current (see figure 1 for filter component values) 1 - high current mode, 300 m a pll loop current (see figure 1 for filter component values) the following bits are read only: auto ac3 and mpeg automatic detection 0 - no ac3/mpeg detected 1 - ac3/mpeg detected on rx/aux du shows selected de-emphasis setting used by dac's 0 - normal flat dac frequency response 1 - de-emphasis selected clke clocking system status 0 - no errors 1 - pll is not locked, crystal is not oscillating, or requesting clock change in progress calp calibration status 1 - calibration in progress 0 - calibration donethis register defaults to 01h this register defaults to 01h note: the ac3 and mpeg detection for the auto bit does not look at the channel status bits. this bit is deter- mined by looking for the ac3/mpeg header in the data stream. see the ac3/mpeg auto detection section earlier in the datasheet for more details. dac control byte (03h) mut6-mut1 mute control bits 0 - normal output level 1 - selected dac output muted mutc controls mute on consecutive zeros function 0 - 512 consecutive zeros will mute dac 1 - dac output will not mute on zeros zcd zero crossing disable 0 - dac mutes and volume control changes occur on zero-crossings. 1 - dac mutes and volume control changes occur immediately. this register defaults to 3fh. b7 b6 b5 b4 b3 b2 b1 b0 calp clke du auto lc 0 cal rs b7 b6 b5 b4 b3 b2 b1 b0 zcd mutc mut6 mut5 mut4 mut3 mut2 mut1
cs4226 ds188f1 23 output attenuator data byte (04h, 05h, 06h, 07h, 08h, 09h) att6-att0 sets attenuator level 0 - no attenuation 127 - 127 db attenuation att0 represents 1.0 db of attenuation this register defaults to 7fh. dac status report byte (read only) (0ah) acc6-acc1 acceptance bit 1 - new setting is waiting for zero-crossing to be accepted. 0 - att6-att0 has been accepted. this register is read-only. adc control byte (0bh) mutl, mutr, mutm - left, right and mono channel mute control 0 - normal output level 1 - selected adc output muted ais1-ais0 adc analog input mux control 0 - selects stereo pair 1 1 - selects stereo pair 2 2 - selects stereo pair 3 3 - differential input is1-is0 input mux selection 0 - stereo adc output to sdout1, mono adc output to sdout2 1 - auxiliary digital input port or s/pdif reciever to sdout1, mono adc output to sdout2 2 - auxiliary digital input port or s/pdif receiver to sdout1, stereo adc output to sdout2 3 - not used. this register defaults to 00h. b7 b6 b5 b4 b3 b2 b1 b0 0 att6 att5 att4 att3 att2 att1 att0 b7 b6 b5 b4 b3 b2 b1 b0 0 - acc6 acc5 acc4 acc3 acc2 acc1 b7 b6 b5 b4 b3 b2 b1 b0 is1 is0 0 ais1 ais0 mutm mutr mutl
cs4226 24 ds188f1 input control byte (0ch) ovrm adc overflow mask 0- error condition is masked at olv/err pin and no dac muting on extended hold 1- no masking vm validity error mask 0- error condition is masked at olv/err pin and no dac muting on extended hold 1- no masking bm biphase error mask 0- error condition is masked at olv/err pin and no dac muting on extended hold 1- no masking pm parity error mask 0- error condition is masked at olv/err pin and no dac muting on extended hold 1- no masking gnl1-gnl0 sets left input gain 0 - 0 db 1 - 3 db 2 - 6 db 3 - 9 db gnr1-gnr0 sets right input gain 0 - 0 db 1 - 3 db 2 - 6 db 3 - 9 db this register defaults to 00h. adc status report byte (read only) (0dh) lvl2-lvl0, lvr2-0 left and right adc output level 0 - normal output levels 1 - -6 db level 2 - -5 db level 3 - -4 db level 4 - -3 db level 5 - -2 db level 6 - -1 db level 7 - clipping lvlm1-lvlm0 mono adc output level 0 - normal output level 1 - -6 db level 2 - -3 db level 3 - clipping these bits are 'sticky'. they constantly monitor the adc output for the peak levels and hold the maximum output. they are reset to 0 when read. this register is read only. b7 b6 b5 b4 b3 b2 b1 b0 ovrm vm bm pm gnr1 gnr0 gnl1 gnl0 b7 b6 b5 b4 b3 b2 b1 b0 lvm1 lvm0 lvr2 lvr1 lvr0 lvl2 lvl2 lvl0
cs4226 ds188f1 25 dsp port mode byte (0eh) ddf2-ddf0 data format 0 - right justified, 20-bit 1 - right justified, 18-bit 2 - right justified, 16-bit 3 - left justified, 20-bit in / 24-bit out 4 - i 2 s compatible, 20-bit in / 24-bit out 5 - one data line mode (fig. 6) 6 - one data line (master mode only, fig. 6) 7 - not used dsck set the polarity of clocking data 0 - data clocked in on rising edge of sclk, out on falling edge of sclk 1 - data clocked in on falling edge of sclk, out on rising edge of sclk dms1-dms0 sets the mode of the port 0 - slave 1 - master burst - sclks are gated 128 fs clocks 2 - master non-burst - sclks are evenly distributed (no 48 fs sclk) 3 - not used - default to slave dck1-dck0 * set number of bit clocks per fs period 0 - 128 1 - 48 - master burst or slave mode only 2 - 32 - all formats will default to 16 bits 3 - 64 this register defaults to 00h. * dck1-dck0 are ignored in formats 5 and 6. b7 b6 b5 b4 b3 b2 b1 b0 dck1 dck0 dms1 dms0 dsck ddf2 ddf1 ddf0
cs4226 26 ds188f1 auxiliary port mode byte (0fh) this byte is not available when the receiver is functioning. adf2-adf0 data format 0 - right justified, 20-bit data 1 - right justified, 18-bit data 2 - right justified, 16-bit data 3 - left justified, 20-bit 4 - i 2 s compatible, 20-bit 5 - not used 6 - not used 7 - not used asck sets the polarity of clocking data 0 - data clocked in on rising edge of sclkaux 1 - data clocked in on falling edge of sclkaux ams1-ams0 sets the mode of the port. 0 - slave 1 - master burst - sclkauxs are gated 128 fs clocks 2 - master non-burst - sclkauxs are evenly distributed in lrckaux frame 3 - not used - default to slave ack1-ack0 set number of bit clocks per fs period. 0 - 128 1 - 48 - master burst or slave mode only 2 - 32 - all input formats will default to 16 bits. 3 - 64 this register defaults to 00h. b7 b6 b5 b4 b3 b2 b1 b0 ack1 ack0 ams1 ams0 asck adf2 adf1 adf0
cs4226 ds188f1 27 auxilliary port control byte (10h) dem 2-0 selects de-emphasis response/source 0 - de-emphasis off 1 - de-emphasis on 32 khz 2 - de-emphasis on 44.1 khz 3 - de-emphasis on 48 khz 4 - de-emphasis pin 32 khz 5 - de-emphasis pin 44.1 khz 6 - de-emphasis pin 48 khz 7 - s/pdif receiver channel status bits dem24 process aux data lsbs 0 - all received data bits (24 max) are processed 1 - top 20 bits processed with de-emphasis filter. 4 aux lsbs are passed unchanged. moh mute on hold 0 - extended hold (16 frames) mutes dac outputs 1 - dacs not muted umv unmute on valid data 0 - dacs unmute when error is removed 1 - dacs must be unmuted in dac control byte after error is removed. hpc hold/rubit pin control 0 - hold/rubit is an input (hold) 1 - hold/rubit is an output(rubit) csp channel status output to pins. 0 - analog inputs to pins. ain2r, ain2l, ain3r, ain3l 1 - channel status to pins. (this forces ais1/0=0) this register defaults to 00h. b7 b6 b5 b4 b3 b2 b1 b0 csp hpc umv moh dem24 dem2 dem1 dem0
cs4226 28 ds188f1 receiver status byte (read only) (11h) par parity bit 0 - no error 1 - error bip biphase bit 0 - no error 1 - error conf confidence bit 0 - no error 1 - error v validity bit 0 - no error 1 - error lock pll lock bit 0 - pll locked 1 - out of lock crc cyclic redundacy check bit 0 - no error 1 - error on either channel cv channel status validity 0 - valid 1 - not valid, data is updating this register is read only. receiver channel status byte (read only) (12h, 13h, 14h, 15h, 16h, 17h, 18h, 19h) byte 12h channel a status byte 1 byte 13h channel a status byte 2 byte 14h channel a status byte 3 byte 15h channel a status byte 4 byte 16h channel b status byte 1 byte 17h channel b status byte 2 byte 18h channel b status byte 3 byte 19h channel b status byte 4 bit definition changes depending upon pro bit setting. when cv = 1, these bits are updating and may be invalid. b7 b6 b5 b4 b3 b2 b1 b0 cv 0 crc lock v conf bip par b7 b6 b5 b4 b3 b2 b1 b0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0
cs4226 ds188f1 29 pin description power supply va+ - analog power input, pin 19. +5 v analog supply. agnd1, agnd2 - analog ground, pins 18, 20. analog grounds. vd+ - digital power input, pin 40. + 5 v digital supply. dgnd1, dgnd2 - digital ground, pins 41, 39. digital grounds. 40 42 34 36 38 6 2 4 8 10 1 3 5 7 9 11 23 25 27 29 31 33 28 24 26 30 32 44 12 14 16 18 20 22 top view dgnd2 vd+ dgnd1 rx1 sclkaux/rx2 lrckaux/rx3 dataux/rx4 hold/rubit scl/cclk sda/cdout ad1/cdin ad0/cs i c/spi pdn ain3r/audio ain3l/autodata ain2l/freq0 ain2r/freq1 ain1r ain1l ainaux cmout 2 sclk lrck sdout1 sdout2 sdin1 sdin2 sdin3 clkout ovl/err xto xti dem aout6 aout5 aout4 aout3 aout2 aout1 agnd2 va+ agnd1 filt
cs4226 30 ds188f1 analog inputs ain1l, ain1r - left and right channel mux input 1, pins 14, 13. analog signal input connections for the right and left channels for multiplexer input 1. ain2l/freq0, ain2r/freq1 - left & right channel mux input 2/channel status freq. bits, pins 11, 12. analog signal input connections for the right and left channels for multiplexer input 2. when csp = 1, these pins are configured as channel status outputs indicating the sampling frequency. ain3l/autodata, ain3r/audio - left & right channel mux input 3/ac3 and mpeg detect output, pins 10, 9. analog signal input connections for the right and left channels for multiplexer input 3. when csp = 1, ain3l is configured as an output indicating the presence of an ac-3 or mpeg data stream at the rx input and ain3r is configured as a channel status output indicating audio/non-audio data at the rx input. ainaux - auxiliary line level input, pin 15. analog signal input for the mono a/d converter. analog outputs aout1, aout2, aout3, aout4, aout5, aout6 - audio outputs, pins 21 - 26. the analog outputs from the 6 d/a converters. each output can be independently controlled for output amplitude. cmout - common mode output, pin 16. this common mode voltage output may be used for level shifting when dc coupling is desired. the load on cmout must be dc only, with an impedance of not less than 50 k w . cmout should be bypassed with a 1.0 m f to agnd. digital audio interface signals sdin1 - serial data input 1, pin 34. digital audio data for the dacs 1 and 2 is presented to the cs4226 on this pin. this pin is also used for one-line data input modes. sdin2 - serial data input 2, pin 33. digital audio data for the dacs 3 and 4 is presented to the cs4226 on this pin. sdin3 - serial data input 3, pin 32. digital audio data for the dacs 5 and 6 is presented to the cs4226 on this pin.
cs4226 ds188f1 31 sdout1- serial data output 1, pin36. digital audio data from the 20-bit stereo audio adcs is output from this pin. when is = 1 or 2, dataaux or the s/pdif receiver is output on sdout1. this pin is also used for one line data output modes. sdout2 - serial data output 2, pin 35. digital audio data from the mono audio adc is output from this pin. when is = 2, the stereo audio adc's are output from this pin sclk - serial port clock i/o, pin 38. sclk clocks digital audio data into the dacs via sdin1/2/3, and clocks data out of the adcs on sdout1/2. active clock edge depends on the dsck bit. lrck - left/right select signal i/o, pin 37. the left/right select signal. this signal has a frequency equal to the sample rate. the relationship of lrck to the left and right channel data depends on the selected format. dem - de-emphasis control, pin 27. when low, dem controls the activation of the standard 50/15 m s de-emphasis filter for either 32, 44.1, or 48 khz sample rates. this pin is enabled by the dem2-0 bits in the auxiliary port control byte. ovl/err - overload indicator, pin 30. this pin goes high if either of the stereo audio adcs or the mono adc is clipping. if the s/pdif receiver is chosen as the clock source (cs = 4, 5, 6, 7), then the pin also goes high if there is an error in the receiver status byte. error and overloading can be masked using bits in the input control byte. auxillary digital audio and s/pdif receiver signals rx1 - receiver channel 1, pin 42. this pin is a dedicated s/pdif input channel configured as the clock source for the device via the cs2-0 bits. dataux/rx4 - auxiliary data input / receiver channel 4, pin 1. dataux is the auxiliary audio data input line, usually connected to an external digital audio source. as rx4, this pin is configured as s/pdif input channel 4 via the control port. lrckaux/rx3 - auxiliary word clock input or output / receiver channel 3, pin 44. in auxiliary slave mode, lrckaux is a word clock (at fs) from an external digital audio source. lrckaux can be used as the clock reference for the internal pll. in auxiliary master mode, lrckaux is a word clock output (at fs) to clock an external digital audio source. as rx3, this pin is configured as s/pdif input channel 3 via the control port.
cs4226 32 ds188f1 sclkaux/rx2 - auxiliary bit clock input or output / receiver channel 2, pin 43. in auxiliary slave mode, sclkaux is the serial data bit clock from an external digital audio source, used to clock in data on dataaux. in auxiliary master mode, sclkaux is a serial data bit clock output. as rx2, this pin is configured as s/pdif input channel 2 via the control port. hold/rubit - s/pdif received user bit / hold control, pin 2. when the s/pdif receiver is chosen as the clock source (cs = 4, 5, 6 and hpc = 1), then this pin outputs the received user bit. when hpc = 0, this pin is sampled on the active edge of sclkaux. if it is high any time during the frame, dataux data is ignored and the previous good sample is output to the serial output port. control port signals i 2 c/spi - control port format, pin 7. setting this pin high configures the control port for the i 2 c interface; a low state configures the control port for the spi interface . the state of this pin sets the function of the control port input/output pins . scl/cclk - serial control interface clock, pin 3. scl/cclk is the serial control interface clock, and is used to clock control bits into and out of the cs4226. ad0/cs - address bit / control port chip select, pin 6. in i 2 c mode, ad0 is a chip address bit. in spi software control mode, cs is used to enable the control port interface on the cs4226. ad1/cdin - address bit / serial control data in, pin 5. in i 2 c mode, ad1 is a chip address bit. in spi software control mode, cdin is the input data line for the control port interface. sda/cdout - serial control data out, pin 4. in i 2 c mode, sda is the control data i/o line. in spi software control mode, cdout is the output data from the control port interface on the cs4226. clock and crystal pins xti, xto - crystal connections, pin 28, 29. input and output connections for the crystal which may be used to operate the cs4226. alternatively, a clock may be input into xti. clkout - master clock output, pin 31. clkout allows external circuits to be synchronized to the cs4226. alternate output frequencies are selectable by the control port.
cs4226 ds188f1 33 miscellaneous pins filt - pll loop filter pin, pin 15. a capacitor, c filt, in series with a resistor, r filt , should be connected from filt to agnd. additionally a capacitor, c rip , should be placed in parallel with c filt and r filt . see figure 1 for recommended component values. pdn - powerdown pin, pin 8. when low, the cs4226 enters a low power mode and all internal states are reset, including the control port. when high, the control port becomes operational and the rs bit must be cleared before normal operation will occur.
cs4226 34 ds188f1 parameter definitions dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 hz to 20 khz), including distortion components. expressed in decibels. adcs are measured at -1dbfs as suggested in aes 17-1991 annex a. idle channel noise / signal-to-noise-ratio the ratio of the rms analog output level with 1 khz full scale digital input to the rms analog output level with all zeros into the digital input. measured a-weighted over a 10 hz to 20 khz bandwidth. units in decibels. this specification has been standardized by the audio engineering society, aes17-1991, and referred to as idle channel noise. this specification has also been standardized by the electronic industries association of japan, eiaj cp-307, and referred to as signal-to-noise-ratio. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. units in decibels. interchannel isolation a measure of crosstalk between channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. frequency response a measure of the amplitude response variation from 20hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units are in decibels. gain error the deviation from the nominal full scale output for a full scale input. gain drift the change in gain value with temperature. units in ppm/c. offset error for the adcs, the deviation in lsbs of the output from mid-scale with the selected input grounded. for the dacs, the deviation of the output from zero (relative to cmout) with mid- scale input code. units are in volts.
cs4226 ds188f1 35 package dimensions inches millimeters dim min max min max a 0.000 0.065 0.00 1.60 a1 0.002 0.006 0.05 0.15 b 0.012 0.018 0.30 0.45 d 0.478 0.502 11.70 12.30 d1 0.404 0.412 9.90 10.10 e 0.478 0.502 11.70 12.30 e1 0.404 0.412 9.90 10.10 e 0.029 0.037 0.70 0.90 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 jedec # : ms-026 44l tqfp package drawing e1 e d1 d 1 e l b a1 a
? notes ?
37 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb4226 evaluation board for cs4226 features l cs4226 - six 20-bit d/a converters, stereo 20-bit a/d converters, mono 20 bit a/d converter, s/pdif receiver l multiple stereo input source selection l input and output of serial audio data through auxiliary and dsp ports l input and output of s/pdif interface signals through coaxial and optical connections l control of cs4226 via spi software interface l multiple clock options available general description the cdb4226 is useful for evaluating the performance of the cs4226. up to three stereo input sources can be connected to the evaluation board, one of which is se- lected for a/d conversion. six channels of d/a conversion allow for multi-channel applications such as dolby pro-logic, dolby digital (ac-3), thx, and dsp- based soundfield applications. s/pdif i/o support is provided by the cs4226s on-chip s/pdif receiver and a cs8402a s/pdif transmitter. for serial audio connec- tions, access to the parts auxiliary and dsp ports is also provided. the board can be configured and controlled by a peripheral serial control port. the peripheral control options are spi and i 2 c. pc software which supports the board's spi interface is provided, and can be used to set the internal control registers of the cs4226. ordering information cdb4226 evaluation board feb 97 ds188db1
cdb4226 38 ds188db1 cdb4226 system overview the cdb4226 evaluation board is designed to al- low thorough evaluation of the cs4226 surround sound codec. six rca jacks allow input of up to three stereo signal sources to the analog input mul- tiplexer of the cs4226, plus one rca jack for a monaural auxiliary input. one of the stereo pairs can be selected for the stereo 20 bit adcs, while the auxiliary input is sent to the mono 20-bit adc. the cs4226 also has six 20-bit dacs, whose out- puts are filtered, buffered, and routed to six rca jacks. digital audio s/pdif signals can be input to the cs4226s s/pdif receiver through optical and coaxial connectors. a cs8402a digital audio transmitter provides optical and coaxial s/pdif outputs. serial audio data i/o is provided by the aux port and the dsp port. both ports can be con- figured to operate with numerous interface formats. the cs4226 supports software control via the spi and i 2 c interfaces. a db-25 connector is provided to allow connection to the serial control port. pc software is provided which establishes an spi in- terface using the pcs printer port. this software provides a means for the user to read and write the control registers on the cs4226. the cdb4226 schematic has been partitioned into 10 small schematics shown in figures 3 through 12. power supply circuitry power is supplied to the evaluation board by six bind- ing posts as shown in figure 3. +5 va and agnd provide 5 volt power to the cs4226. the +/-12 v binding posts provide power to the analog input and output buffers. the +5 vd and gnd binding posts supply 5 volt power to the digital section of the board. all power supply connections are equipped with tran- sient suppression diodes and bulk filtering capacitors. analog inputs the cs4226 is capable of switching between three stereo pairs of line level inputs, and is equipped with a mono auxiliary input. the desired input is selected by setting the ais1/0 bits in the adc control byte and the csp bit in the aux port control byte (con- sult the cs4226 data sheet for details on the config- uration registers). the seven analog inputs (ain1l, ain1r, ain2l, ain2r, ain3l, ain3r, and ain- aux) are low-pass filtered and buffered, as shown in figures 4 and 5 (-3 db at 200 khz). the ac cou- pling caps (c56-c62) allow the input pins of the cs4226 to self-bias to approximately 2.3 volts. a nominal amplitude of 1 vrms to these inputs will achieve a full scale digital output from the a/d con- verters in the cs4226. all inputs are noninverting. ain1l, ain1r, and ainaux are dedicated ana- log input connections to the cs4226. however, ain2l, ain2r, ain3l, and ain3r can also func- tion as digital outputs (figure 5). the output names are freq0, freq1, autodata, and /audio, respectively. when configured as outputs, these pins provide channel status information from the on-chip s/pdif receiver (consult the cs4226 data sheet for details on pinout functionality). the status of these pins can be monitored with the leds pro- vided (d8-d9). the four jumpers hdr5-hdr8, defined in table 1, are used in conjunction with the csp bit in the auxiliary port control byte to con- figure these pins. when the csp bit is a logic low, the pins become analog inputs. in this configura- tion, hdr5-hdr8 should be placed in the ain po- sition. when the csp bit is a logic high, the pins become digital outputs; in this case hdr5-hdr8 should be placed in the csout position. note that the four jumpers should each be set to the same cor- responding position. the cs4226 also supports a differential input mode in which the single-ended inputs ain3l and ain2l become differential inputs ainl+ and ainl-, respectively. likewise, the single-ended
cdb4226 ds188db1 39 inputs ain2r and ain1r become differential in- puts ainr- and ainr+, respectively. selection of the differential mode is made with the ais1/0 bits in the adc control byte. the balanced input con- figuration can be tested using special cables which have a male xlr connector on one end and a pair of rca connectors on the other end. analog outputs the six dac outputs, aout1-aout6, are passed through a 2-pole butterworth low-pass filter and are ac coupled, as shown in figure 6 (-3 db at 44.1 khz). each output will produce a nominal 1 vrms output for a full scale digital input. note that the filter outputs, out1-out6, are noninverting. the output filters in figure 6 have additional resis- tor and capacitor sockets to accomodate a 3-pole butterworth filter this may be useful if increased out-of-band noise filtering is desired. the cs4226 provides a common mode biasing voltage of approximately 2.3 v on its cmout pin. the cdb4226 analog inputs and outputs are ac coupled, and hence cmout is not required on the input and output filter stages. since other filter to- pologies may need a common mode bias voltage, a buffered version of cmout is available on the test point labeled cmoutfo (figure 4). clock configurations the timing on the board should be generated by a single clock source, with the dsp port and aux port operating synchronously to the selected clock source. operating the serial audio interfaces at clock frequencies which deviate from each other will cause the cs4226 to reset its data paths in an attempt to resynchronize. potential clock sources are: 1) the recovered clock from the s/pdif receiver on the cs4226, table 1. jumper-selectable options jumper purpose position function selected hdr5, hdr6, hdr7, hdr8 sets the direction of ain3r/audio, ain3l/autodata, ain2l/freq0, and ain2r/freq1. all four jumpers must be set to the same position, and corre- spond with the csp bit in aux port control byte. ain csout pins 9-12 on cs4226 are analog inputs (csp=0). pins 9-12 on cs4226 are channel status out- puts (csp=1). xt_sel selects the configuration for the xt pin on the dsp port. jumper position must correspond with the dms1/0 bits in the dsp port mode byte and with the direc- tion of the transceiver, u16. xtin xtal xtout xt is input to xti. y1 must be removed. u16 must be configured as input. xt is disconnected from xti/xto and is grounded through 47k resistor. xt outputs xto clock from cs4226. u16 must be configured as output. rx_sel routes s/pdif datastream from rx_opt to one of three s/pdif receiver input pins on the cs4226, rx2, 3, or 4. jumper position must cor- respond with the cs2/1/0 bits in the clock mode byte. rx2 rx3 rx4 rx_auxb sends optical input to rx2 of cs4226. sends optical input to rx3 of cs4226. sends optical input to rx4 of cs4226. configures board for aux port input. clk_sel tristates clkout1 on aux_hdr, allowing aux_hdr to be compatible with 10-pin serial data connectors found on other crystal cdb capture boards. clkoff clkout1 tristates clkout1 buffer on u3. enables clkout1 buffer on u3.
cdb4226 40 ds188db1 2) the lrck or lrckaux inputs to the cs4226, 3) a 1 fs, 256 fs, 384 fs, or 512 fs crystal con- nected between xti and xto on the cs4226, or 4) a 1 fs, 256 fs, 384 fs, or 512 fs clock connect- ed to xti on the cs4226 from the xt clock line on the dsp port, dsp_hdr. the clock source is chosen by setting the clock source bits, cs2/1/0 in the clock mode byte, and by configuring the xt_sel jumper, defined in ta- ble 1, to the appropriate position, as described be- low. xt_sel jumper and xt clock line when the master clock for the board is derived from methods (1), (2), or (3), the xt_sel jumper may be set to the xtal position. this position disconnects the xt clock line on the dsp port (fig- ure 9) from the xti/xto clock and crystal pins of the cs4226 (figure 7). in case (3), the xt line can be set up to output the xto signal from the cs4226. this configuration makes a buffered version of the crystal clock fre- quency available on the dsp port. this is accom- plished by setting xt_sel to the xtout position, and by configuring the bidirectional clock lines, xt, sclk, and lrck, to be outputs. the pc software can be used to set the dms 1/0 bits in the dsp port mode byte to 01 or 10, making the clock lines outputs on the cs4226. the pc software also generates a control line called sp_buf, which con- trols the direction of the bidirectional transceiver, u16 (figure 8). care must be taken to ensure that the dms bit settings correspond to the direction set by the software control line. details on the soft- ware are given in the last section of this datasheet. in case (4), the xt line can serve as the master clock source for the cdb4226. to configure the board in this manner, set the xt_sel jumper to the xtin position. additionally, the xt, sclk, and lrck lines on the dsp port must be configured as inputs to the evaluation board. the pc software is used to set the dms1/0 bits to 00 (lrck and sclk are inputs). also, the software is used to set the direction of the bidirectional buffer, u16, so that xt, sclk, and lrck are buffered onto the board. notice that when xt is used as an external master clock source for the board, the sclk and lrck lines cannot be outputs. sclk and lrck must be sourced externally. digital inputs the cs4226 can accept digital audio signals in ei- ther serial form or s/pdif form. the cs2/1/0 bits in the clock mode byte are used in conjunction with the rx_sel jumper (defined in table 1) to config- ure the board for serial or s/pdif data sources. serial input interface serial data can be received through the aux port header, aux_hdr (figure 8), which provides ac- cess to the aux port of the cs4226. the four clock and data lines on aux_hdr are defined in table 2. the cs4226 will accept serial data through the aux port by setting the cs2/1/0 bits in the clock mode byte to 0, 1, 2, or 3 (hex), and by moving the rx_sel jumper to the rx_auxb position. notice that the lrclkaux and sclkaux lines on the aux port are bidirectional. the ams1/0 bits in the auxiliary port mode byte determine the direction of the lrclkaux and sclkaux lines. the pc software generates a control line called aux_buf, which controls the direction of the bidirectional transceiver, u23 (figure 8). care must be taken to ensure that the ams bits corre- spond to the direction set by the software control line. details on the software are given in the last section of this datasheet. a buffered version of clkout, called clkout1, is available on aux_hdr. clkout frequencies of 1 fs, 256 fs, 384 fs, and 512 fs can be selected using the co1/0 bits in the clock mode
cdb4226 ds188db1 41 byte. this clock line is useful for synchronizing external a/d converters or other peripheral compo- nents. clkout1 can be tristated by selecting the position of the clk_sel jumper, defined in table 1. this feature may be useful in interfacing other crystal evaluation boards (cdb5330a and cdb5334/35 for example) to the cdb4226, as it prevents a drive contention on the mclk output of these boards. s/pdif input interface the optical and coaxial digital inputs labeled rx_opt and rx_dig (figure 8) allow access to the on-chip s/pdif receiver, which can receive and decode one of four s/pdif input sources. setting the cs2/1/0 bits in the clock mode byte to 4, 5, 6, or 7 (hex) will configure the cs4226 to choose rx1, rx2, rx3, or rx4, respectively, as the s/pdif input source. the coaxial input, rx_dig, is dedicated to the rx1 input on the cs4226. the optical input, rx_opt, can be routed to one of the three other s/pdif receiver input pins by using the rx_sel jumper. setting rx_sel to the rx2, rx3, or rx4 position will route the s/pdif data from the optical input to the rx2, rx3, or rx4 pin of the codec. connector name connector type input / output signal present +5 va binding post input +5 volts for analog section +5 vd binding post input +5 volts for digital section +/- 12 v binding post input +/- 12 volts for analog input and output buffers agnd binding post input analog ground connection from power source gnd binding post input digital ground connection from power source ain1l, ain1r rca inputs left and right channel analog inputs, 1st stereo pair ain2l, ain2r rca inputs left and right channel analog inputs, 2nd stereo pair ain3l, ain3r rca inputs left and right channel analog inputs, 3rd stereo pair ainaux rca input auxiliary analog input out1 - out6 rca outputs six buffered and filtered dac output channels rx_dig rca input coaxial input to rx1 of cs4226 s/pdif receiver rx_opt toslink input optical input to rx2, 3, or 4 of cs4226 s/pdif receiver 8402_dig rca output cs8402a digital output via transformer 8402_opt toslink output cs8402a digital output via optical transmitter dataux header (aux_hdr) input aux port serial data input lrclkaux, sclkaux header (aux_hdr) inputs/outputs i/o for aux port serial and left/right clocks clkout1 header (aux_hdr) output buffered clkout from cs4226 scl/cclk1 header (dsp_hdr) input serial control clock for i 2 c interface sda/cdout1 header (dsp_hdr) bidirectional control data i/o line for i 2 c interface sdin1, sdin2, sdin3 header (dsp_hdr) inputs dsp port serial data inputs xt header (dsp_hdr) input/output dsp port xti input access, or buffered xto from cs4226 clkout header (dsp_hdr) output buffered clkout from cs4226 lrck, sclk header (dsp_hdr) inputs/outputs i/o for dsp port serial and left/right clocks sdout1, sdout2 header (dsp_hdr) outputs dsp port serial data outputs pc conn db-25 inputs/outputs db-25 connector to pc for spi/i 2 c control port signals table 2. system connections
cdb4226 42 ds188db1 dsp port the dsp port header, dsp_hdr, provides access to the dsp port of the cs4226. the eleven clock, control, and data lines are defined in table 2. the xt, sclk, and lrck lines can be inputs or out- puts, and their i/o configuration is defined in the clock configuration section above. clkout, sdout1, and sdout2 are buffered outputs from the cs4226. the serial data input lines, sdin1, 2, and 3, provide external access to the sdin1, 2, and 3 pins of the cs4226. the i 2 c interface lines, la- beled sda/cdout1 and scl/cclk1, allow configuration of the cs4226 registers without hav- ing to use the pc connector, pc conn. the altera epm7032 programmable logic device (pld), shown in figure 11, is used to route serial audio data in several ways on the board. the switches on s2 labeled sdin_m2/m1/m0 (figure 11) select the input to the sdin1, 2 and 3 pins of the cs4226. the various routing schemes are de- fined in table 3. there are seven loopback config- urations which are selected by setting sdin_m2/m1/m0 to 0-6 (hex). to access the sdin pins on the codec from the dsp port header, sdin_m2/m1/m0 should be set to 7 (hex). s/pdif output a cs8402a digital audio transmitter, shown in figure 9, allows serial data from either sdout1 or sdout2 to be transmitted in s/pdif form through an optical transmitter (8402_opt) and through an rca connector (8402_dig). the transmitter pro- vides a convenient way to evaluate the perfor- mance of the a/d converters on the cs4226. the dip switches sw1 and s2 (figure 9) configure the pld to adjust the clock and data outputs of the cs4226 to the format requirements of the cs8402a. the functionality of each switch is de- scribed below. cs8402a mclk generation the clkout signal of the cs4226 can be 1 fs, 256 fs, 384 fs, or 512 fs. the cs8402a requires a master clock frequency of 128 fs to operate. when clkout is 1 fs, the cs8402a will be in- operable. however, to accomodate the other possi- ble frequencies of clkout, the evaluation board can be configured to divide clkout by 2, 3, or 4 to generate a 128 fs master clock for the transmit- ter. the switches on sw1 labeled mclk_s1 and mclk_s0 select the degree of clock division as defined in table 3. cs8402a format selection the five switches on sw1 and s2 labeled sp_rising, sp_l_rb, bits1, bits0, and i2s are used to select the correct digital interface for- mat for the cs8402a. these switches are defined in table 3. their settings must correspond with the dsck and ddf2/1/0 bits in the dsp port mode byte register. table 4 shows which dsp port mode byte settings the cs8402a can support for s/pdif transmission. all other settings not listed in the table are not valid. sdoutx output selection the switch on s2 labeled sdout_m0 selects the source of data to the cs8402a. a logic low selects sdout1 for transmission, and a logic high selects sdout2.
cdb4226 ds188db1 43 sw1 switch # 0 = closed, 1 = open comment 6, 5 mclk_s1, mclk_s0 divides clkout to generate mclk_8402 for cs8402a transmitter. 0 0 generates a 128 fs clock when clkout = 256 fs (co = 0). 0 1 reserved 1 0 generates a 128 fs clock when clkout = 384 fs (co = 1). 1 1 generates a 128 fs clock when clkout = 512 fs (co = 2). 4 sp_rising selects sclk valid data edge. this bit must agree with dsck bit in dsp port mode byte. 0 data is clocked into cs8402a on falling edge of sclk (dsck = 1). 1 data is clocked into cs8402a on rising edge of sclk (dsck = 0). 3 sp_l_rb selects left or right justified data. this bit must agree with ddf bits in dsp port mode byte. 0 serial data lines are right justified (ddf = 0,1,2). 1 serial data lines are left justified (ddf 1 0,1,2). 2, 1 bits1, bits0 selects bits of resolution. these bits must agree with ddf bits in dsp port mode byte. 0 0 16 bits (ddf = 2) 0 1 18 bits (ddf = 1) 1 0 20 bits (ddf = 0, 3) 1 1 reserved s2 switch # 0 = closed, 1 = open comment 5 i 2 s selects i 2 s compatible mode. this bit must agree with ddf bits in dsp port mode byte. 0 i 2 s mode off (ddf 1 4). 1 i 2 s mode on (ddf = 4). 4 sdout_m0 selects the source of data to the cs8402a. 0 sdout1 from cs4226 is routed to sdata pin of cs8402a. 1 sdout2 from cs4226 is routed to sdata pin of cs8402a. 3, 2, 1 sdin_m2, sdin_m1, sdin_m0 selects the source of data to sdin1, 2, and 3 on the cs4226. choices are sdout lines from the cs4226, sdin lines from dsp_hdr, or zeros. 0 0 0 sdout1 => sdin1, 0 => sdin2, 0 => sdin3 0 0 1 0 => sdin1, sdout1 => sdin2, 0 => sdin3 0 1 0 0 => sdin1, 0 => sdin2, sdout1 => sdin3 0 1 1 sdout1 => sdin1, sdout1 => sdin2, sdout1 => sdin3 1 0 0 sdout2 => sdin1, sdout2 => sdin2, sdout2 => sdin3 1 0 1 sdout1 => sdin1, sdout1 => sdin2, sdout2 => sdin3 1 1 0 sdout1 => sdin1, sdout2 => sdin2, sdout2 =>sdin3 1 1 1 sdin1_hdr =>sdin1, sdin2_hdr =>sdin2, sdin3_hdr =>sdin3 table 3. dip switch definitions
cdb4226 44 ds188db1 dsp port mode byte 1 = open, 0 = closed, x = don't care, n/a = not available sw1: #4 sw1: #3 sw1: #2, #1 s2: #5 (hex) descriptor sp_rising sp_l_rb bits1/ bits0 i 2 s dck1-dck0 = 00, 01, or 11 => 128, 48, or 64 bit clocks per fs period. 01, 41, c1 cs4226 slave, valid data on sclk rising edge, right-justified, 18 bit 1 0 01 0 02, 42, c2 cs4226 slave, valid data rising edge, right-justified, 16 bit 1 0 00 0 03, 43, c3 cs4226 slave, valid data rising edge, left-justified, 20 bit in, 24 bit out 1 1 10 0 04, 44, c4 cs4226 slave, valid data rising edge, i 2 s, 20 bit in, 24 bit out 1xxx1 09, 49, c9 cs4226 slave, valid data on sclk falling edge, right-justified, 18 bit 0 0 01 0 0a, 4a, ca cs4226 slave, valid data falling edge, right-justified, 16 bit 0 0 00 0 0b, 4b, cb cs4226 slave, valid data falling edge, left-justified, 20 bit in, 24 bit out 0 1 10 0 0c, 4c, cc cs4226 slave, valid data falling edge, i 2 s, 20 bit in, 24 bit out 0 x xx 1 11, 51, d1 cs4226 master burst, valid data on sclk rising edge, right-justified, 18 bit 1 0 01 0 12, 52, d2 cs4226 master burst, valid data rising edge, right-justified, 16 bit 1 0 00 0 13, 53, d3 cs4226 master burst, valid data rising edge, left-justified, 20 bit in, 24 bit out 1 1 10 0 14, 54, d4 cs4226 master burst, valid data rising edge, i 2 s, 20 bit in, 24 bit out 1 x xx 1 19, 59, d9 cs4226 master burst, valid data on sclk falling edge, right-justified, 18 bit 0 0 01 0 1a, 5a, da cs4226 master burst, valid data falling edge, right-justified, 16 bit 0 0 00 0 1b, 5b, db cs4226 master burst, valid data falling edge, left-justified, 20 bit in, 24 bit out 0 1 10 0 1c, 5c, dc cs4226 master burst, valid data falling edge, i 2 s, 20 bit in, 24 bit out 0xxx1 21, e1 cs4226 master nonburst, valid data on sclk rising edge, right-justified, 18 bit 1 0 01 0 22, e2 cs4226 master nonburst, valid data rising edge, right-justified, 16 bit 1 0 00 0 23, e3 cs4226 master nonburst, valid data rising edge, left-justified, 20 bit in, 24 bit out 1 1 10 0 24, e4 cs4226 master nonburst, valid data rising edge, i 2 s, 20 bit in, 24 bit out 1xxx1 29, e9 cs4226 master nonburst, valid data on sclk falling edge, right-justified, 18 bit 0 0 01 0 2a, ea cs4226 master nonburst, valid data falling edge, right-justified, 16 bit 0 0 00 0 2b, eb cs4226 master nonburst, valid data falling edge, left-justified, 20 bit in, 24 bit out 0 1 10 0 2c, ec cs4226 master nonburst, valid data falling edge, i 2 s, 20 bit in, 24 bit out 0xxx1 dck1-dck0 = 10 =>32 bit blocks per fs period (all formats default to 16 bits) 80, 81, 82 cs4226 slave, valid data on sclk rising edge, right-justified,16 bit 1 0 00 0 83 cs4226 slave, valid data rising edge, left-justified, 16 bit 1 1 xx 0 84 cs4226 slave, valid data rising edge, i 2 s, 16 bit 1 x xx 1 88, 89, 8a cs4226 slave, valid data on sclk falling edge, right-justified, 16 bit 0 0 00 0 8b cs4226 slave, valid data falling edge, left-justified, 16 bit 0 1 00 0 8c cs4226 slave, valid data falling edge, i 2 s, 16 bit 0 x xx 1 90, 91, 92 cs4226 master burst, valid data on sclk rising edge, right-justified, 16 bit 1 0 00 0 93 cs4226 master burst, valid data rising edge, left-justified, 16 bit 1 1 00 0 94 cs4226 master burst, valid data rising edge, i 2 s, 16 bit 1 x xx 1 98, 99, 9a cs4226 master burst, valid data on sclk falling edge, right-justified, 16 bit 0 0 00 0 9b cs4226 master burst, valid data falling edge, left-justified, 16 bit 0 1 00 0 9c cs4226 master burst, valid data falling edge, i 2 s, 16 bit 0xxx1 a0, a1, a2 cs4226 master nonburst, valid data on sclk rising edge, right-justified, 16 bit 1 0 00 0 a3 cs4226 master nonburst, valid data rising edge, left-justified, 16 bit 1 1 00 0 a4 cs4226 master nonburst, valid data rising edge, i 2 s, 16 bit 1xxx1 a8, a9, aa cs4226 master nonburst, valid data on sclk falling edge, right-justified, 16 bit 0 0 00 0 ab cs4226 master nonburst, valid data falling edge, left-justified, 16 bit 0 1 00 0 ac cs4226 master nonburst, valid data falling edge, i 2 s, 16 bit 0xxx1 table 4. dsp port formats supported by cs8402a transmitter
cdb4226 ds188db1 45 spi control port software the spi/i 2 c port can be accessed through the db- 25 connector, pc conn. software is provided which allows reading and writing of the cs4226 control port registers with a pc using the spi for- mat. the supplied cable should be attached be- tween pc conn and the pc parallel port. software description four c programs have been compiled to operate under ms-dos. these programs can be run direct- ly from the floppy disk provided. a brief descrip- tion of the supplied routines is given. to see a full argument list for each routine, simply type the command with no arguments. rstspi send a brief reset to the board. this is the same as depressing the /pdn switch. rdspi this routine returns the value located in the register pointed to by . the value is in hex and the value returned is in hex. wrspi this routine writes the into the register pointed to by . both values are in hex. dumpspi this routine dumps the value of all the registers starting at up to register 25. rdpsi, wrspi, and dumpspi have an optional argument "-pxx", defined in table 5. this argu- ment is used to set the direction of the bidirectional transceivers, u23 (figure 8) and u16 (figure 9). the "-pxx" argument must be sent at least once after powerup to configure the evaluation board to recognize whether the aux port and dsp port are in master mode (clock lines are outputs) or in slave mode (clock lines are inputs). the "-pxx" argu- ment should be set with consideration of setting the dms bits in the dsp port mode byte and the ams bits in the auxiliary port mode byte. optional argument description -p00 cs4226 aux port is master, dsp port is master (user must set ams=2, dms=2) -p08 cs4226 aux port is master, dsp port is slave (user must set ams=2, dms=0) -p10 cs4226 aux port is slave, dsp port is master (user must set ams=0, dms=2) -p18 cs4226 aux port is slave, dsp port is slave (user must set ams=0, dms=0) -e specifies an ending register on dumpspi table 5. optional software switch statements for rdspi, wrspi, and dumpspi commands
cdb4226 46 ds188db1 pre-configured setups for ease of implementation, batch files are provid- ed along with the required jumper and dip switch settings for two modes of operation. choice of op- eration mode is based primarily on the desired source of the data. all jumper settings not men- tioned remain unchanged. 1: receiver mode the clock source is a recovered clock from the s/pdif coax input, rx_dig. recovered data is transmitted by the cs8402a. additionally, sdout1 data is looped back to the dacs. type "powuprx1" at the appropriate prompt to run the batch file for this mode of operation. signal flow: dip switch settings: located on s2 sdin_m0 - 1 = >open sdin_m1 - 1 = >open sdin_m2 - 0 = >closed sdout_m0 -0 = >closed i 2 s - 0 = >closed located on sw1 bits0 - 0 = >closed bits1 -1 = > open sp_l_rb - 1 = >open sp_rising - 0 = >closed mclk_s0 - 0 = >closed mclk_s1 - 0 = >closed jumper settings: xt_sel - xtal rx_sel - rx2, rx3 or rx4 hrdr5,6,7,8 - csout batch file: powuprx1.bat 2: crystal mode the clock source is a crystal (y1). stereo adc out- put data is transmitted by the cs8402a. sdout1 data is looped back to the dacs. the stereo signal is applied to stereo pair 1 on the evaluation board (ain1l/r). type "powupxtl" at the appropriate prompt to run the batch file for this mode of opera- tion. figure 1. cdb4226 in receiver mode
cdb4226 ds188db1 47 signal flow: dip switch settings: located on s2 sdin_m0 - 1 = >open sdin_m1 - 1 = >open sdin_m2 - 0 = >closed sdout_m0 - 0 = >closed i 2 s - 0 = >closed located on swi bits0 - 0 = >closed bits1 - 1 = >open sp_l_rb - 1 = >open sp_rising - 0 = >closed mclk_s0 - 0 = >closed mclk_s1 - 0 = >closed jumpersettings: hrdr5,6,7,8 - ain xt_sel - xtal batch file: powupxtl.bat figure 2. cdb4226 in crystal mode
cdb4226 48 ds188db1 figure 3. power supply and bulk filtering
cdb4226 ds188db1 49 figure 4. dedicated analog inputs
cdb4226 50 ds188db1 figure 5. analog inputs/channel status outputs with led indicators
cdb4226 ds188db1 51 figure 6. analog outputs
cdb4226 52 ds188db1 figure 7. cs4226
cdb4226 ds188db1 53 figure 8. aux port and s/pdif inputs
cdb4226 54 ds188db1 figure 9. dsp port figure 10. cs8402a digital audio transmitter
cdb4226 ds188db1 55 figure 11. altera pld and dip switches
cdb4226 56 ds188db1 figure 12. spi/i 2 c control port interface
cdb4226 ds188db1 57 figure 13. cdb4226 rev. b silkscreen (not to scale)
cdb4226 58 ds188db1 figure 14. cdb4226 rev. b component side (not to scale)
cdb4226 ds188db1 59 figure 15. cdb4226 rev. b solder side (not to scale)

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